1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a dual salicidation process which can form a silicide gate conductor having a greater thickness than silicide structures formed upon source and drain regions. A high K gate dielectric residing between the gate conductor and the substrate substantially inhibits consumption of the junctions during formation of the silicide gate conductor.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been placed into a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the impurity regions. Interconnect routing is then placed across the semiconductor topography and connected to the impurity regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. The entire process of making ohmic contacts to the impurity regions and/or the gate areas and routing interconnect material between the ohmic contacts is generally described as "metallization". As the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased. Conductive materials other than metal are commonly used for metallization. As such, the term metallization is generic in its application.
Integrated circuits often employ active devices known as transistors. A transistor includes a pair of impurity regions, i.e., junctions, spaced apart by a gate conductor. The gate conductor is dielectrically spaced above a semiconductor substrate within which the junctions reside. The junctions contain dopants which are opposite in type to the dopants residing within a channel region of the substrate interposed between the junctions. The gate conductor typically comprises polycrystalline silicon ("polysilicon") which is rendered conductive by implanting dopants therein. Polysilicon can withstand relatively high temperatures. Therefore, a polysilicon gate conductor may be formed prior to performing high-temperature anneal steps, such as the post-implant anneal of the junctions. As such, the gate conductor may be patterned before the source and drain junctions are formed and annealed. In fact, the gate conductor is commonly used as a channel region mask during the formation of the source and drain junctions. One of the disadvantages of using polysilicon as the gate conductor material, however, is that it has a significantly higher resistivity than metals, such as aluminum. The propagation delay of an integrated circuit employing a polysilicon gate conductor thus may be longer than desired. Consequently, the operational frequency that can be achieved by a circuit employing a polysilicon gate conductor is somewhat limited.
The formation of ohmic contacts through an interlevel dielectric involves using a technique known as lithography to pattern a protective mask (i.e., photoresist) upon areas of the dielectric exclusive of where the contacts are to be formed. The areas of the interlevel dielectric left uncovered by the mask are then etched to form openings or "windows" through the interlevel dielectric to underlying junctions and gate conductors. The contact windows are filled with a conductive material to complete formation of the contacts. Unfortunately, the mask may be misaligned relative to the underlying topography during the lithography process. Accordingly, the contacts may be shifted from their targeted positions directly above the junctions and the gate conductors. As a result of the misalignment, the contact/junction and contact/gate conductor interfaces may experience increased contact resistances. The parasitic series resistances of the source and drain contact structures thus may be high enough to detrimentally affect the drive current of transistors employed by the integrated circuit.
To reduce the contact resistances at the contact/junction and contact/gate conductor interfaces, self-aligned low resistivity structures are commonly placed between the ohmic contacts and the junctions/gate conductors. The presence of these so-called self-aligned silicides (i.e., salicides) upon the junctions and gate conductors ensures that contact is made to the entire junction and gate areas. Further, forming salicide upon a polysilicon gate conductor helps lower the sheet resistance of the gate conductor. Salicide formed upon polysilicon is generally referred to as polycide. A salicide process involves depositing a refractory metal across the semiconductor topography, and then reacting the metal only in regions where a high concentration of silicon atoms are present. In this manner, salicides may be formed exclusively upon the junctions and the upper surfaces of polysilicon gate conductors. The sidewall surfaces which bound the gate conductors may be pre-disposed with dielectric sidewall spacers. The sidewall spacers serve to prevent the refractory metal from contacting, and hence reacting with, the polysilicon at the sidewall surfaces of the gate conductor. Absent the sidewall spacers, silicide could form upon the sidewall surfaces of the silicon-based gate conductors, undesirably shorting the gate conductors to adjacent junctions.
Transistor device dimensions have been continuously reduced to accommodate the high demand for faster, more complex integrated circuits. As such, the source and drain junction depths have been reduced. Unfortunately, a salicide may completely consume a relatively shallow junction and penetrate into the substrate underneath the junction, a phenomenon known as "junction spiking". Junction spiking may undesirably cause the junction to exhibit large current leakage or become electrically shorted. Therefore, in order to prevent excessive consumption of shallow junctions during contact formation, the junction salicide can only be of limited thickness. Since the gate and junction salicides are formed at the same time, the gate salicide also has a limited thickness. However, it is desirable to form a relatively thick layer of salicide upon a gate conductor to lower the sheet resistance of the gate conductor. Accordingly, it would be of benefit to develop a salicidation process in which the junction salicides and the gate salicides have dissimilar thicknesses. That is, the salicidation process must no longer require concurrent formation of the junction salicides and the gate salicides.